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<div class="title">xxxvethernet_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga739e90cc435465f16f1c78705a69e7e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#ga739e90cc435465f16f1c78705a69e7e5">XXxvEthernet_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + (RegOffset))))</td></tr>
<tr class="memdesc:ga739e90cc435465f16f1c78705a69e7e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">XXxvEthernet_ReadReg returns the value read from the register specified by <em>RegOffset</em>.  <a href="group__xxvethernet.html#ga739e90cc435465f16f1c78705a69e7e5">More...</a><br/></td></tr>
<tr class="separator:ga739e90cc435465f16f1c78705a69e7e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8fe72cb95db1fbc60514b6485020108"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#gaf8fe72cb95db1fbc60514b6485020108">XXxvEthernet_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td></tr>
<tr class="memdesc:gaf8fe72cb95db1fbc60514b6485020108"><td class="mdescLeft">&#160;</td><td class="mdescRight">XXxvEthernet_WriteReg, writes <em>Data</em> to the register specified by <em>RegOffset</em>.  <a href="group__xxvethernet.html#gaf8fe72cb95db1fbc60514b6485020108">More...</a><br/></td></tr>
<tr class="separator:gaf8fe72cb95db1fbc60514b6485020108"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XXV Ethernet registers offset</div></td></tr>
<tr class="memitem:ga0a0a558e7c5b10528d5b54e108a98e2c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0a0a558e7c5b10528d5b54e108a98e2c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_GRR_OFFSET</b>&#160;&#160;&#160;0x00000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RST_OFFSET</b>&#160;&#160;&#160;0x00000004</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_MODE_OFFSET</b>&#160;&#160;&#160;0x00000008</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_TXCFG_OFFSET</b>&#160;&#160;&#160;0x0000000C</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXCFG_OFFSET</b>&#160;&#160;&#160;0x00000014</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXMTU_OFFSET</b>&#160;&#160;&#160;0x00000018</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_TICK_OFFSET</b>&#160;&#160;&#160;0x00000020</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_REV_OFFSET</b>&#160;&#160;&#160;0x00000024</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_AN_OFFSET</b>&#160;&#160;&#160;0x000000C8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RSFEC_OFFSET</b>&#160;&#160;&#160;0x000000D0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_FEC_OFFSET</b>&#160;&#160;&#160;0x000000D4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_ANCR1_OFFSET</b>&#160;&#160;&#160;0x000000E0</td></tr>
<tr class="separator:gafbd5912304e614171e5666d60cc96991"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_ANCR2_OFFSET</b>&#160;&#160;&#160;0x000000E4</td></tr>
<tr class="separator:ga22578e7768357fff639e66c7c855368f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_ANACR_OFFSET</b>&#160;&#160;&#160;0x000000F8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_LTCR_OFFSET</b>&#160;&#160;&#160;0x00000100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_LTTR_OFFSET</b>&#160;&#160;&#160;0x00000104</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_LTPR_OFFSET</b>&#160;&#160;&#160;0x00000108</td></tr>
<tr class="separator:ga9a539966e09ba9267bf0c1f07020cc59"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_LTIR_OFFSET</b>&#160;&#160;&#160;0x0000010C</td></tr>
<tr class="separator:gacf0d2c37799d00671ec3e17dbafedfbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_LTSR_OFFSET</b>&#160;&#160;&#160;0x00000110</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_LTCOR_OFFSET</b>&#160;&#160;&#160;0x00000130</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USR0_OFFSET</b>&#160;&#160;&#160;0x00000184</td></tr>
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<tr class="memitem:gaf7a0881396d27e8ed2167a834174b6fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf7a0881396d27e8ed2167a834174b6fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USR1_OFFSET</b>&#160;&#160;&#160;0x00000188</td></tr>
<tr class="separator:gaf7a0881396d27e8ed2167a834174b6fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Xxv Ethernet status registers offset</div></td></tr>
<tr class="memitem:ga015e1e902b4a017a14512bc0b0d13b1a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga015e1e902b4a017a14512bc0b0d13b1a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_CORESPEEDSR_OFFSET</b>&#160;&#160;&#160;0x00000180</td></tr>
<tr class="separator:ga015e1e902b4a017a14512bc0b0d13b1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c14aaebd1af2c8d9c47c9c9bde74258"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c14aaebd1af2c8d9c47c9c9bde74258"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_TXSR_OFFSET</b>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="separator:ga1c14aaebd1af2c8d9c47c9c9bde74258"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86fad2f6ff049cf5392119dc30329f7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga86fad2f6ff049cf5392119dc30329f7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXSR_OFFSET</b>&#160;&#160;&#160;0x00000404</td></tr>
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<tr class="memitem:ga6990931f617719cce1bd2aaa2d989254"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6990931f617719cce1bd2aaa2d989254"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_SR_OFFSET</b>&#160;&#160;&#160;0x00000408</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXBLSR_OFFSET</b>&#160;&#160;&#160;0x0000040C</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_ANSR_OFFSET</b>&#160;&#160;&#160;0x00000458</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_ANASR_OFFSET</b>&#160;&#160;&#160;0x0000045C</td></tr>
<tr class="separator:ga3433e98c005d06088a47f78c10c3df5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">MODE register masks</div></td></tr>
<tr class="memitem:ga2608ebc122b8df59f3461bc030dedc1e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2608ebc122b8df59f3461bc030dedc1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_MODE_LCLLPBK_MASK</b>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="separator:ga2608ebc122b8df59f3461bc030dedc1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TXCFG register masks</div></td></tr>
<tr class="memitem:gaa84df738fdf445b03046539bfc84b4ac"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa84df738fdf445b03046539bfc84b4ac"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_TXCFG_TX_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:gaa84df738fdf445b03046539bfc84b4ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06f89cd9f998c0cc8e62240e315550ed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga06f89cd9f998c0cc8e62240e315550ed"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_TXCFG_FCS_MASK</b>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="separator:ga06f89cd9f998c0cc8e62240e315550ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RXCFG register masks</div></td></tr>
<tr class="memitem:gaa6ee4fc8b094860e86dee1d747dc2015"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa6ee4fc8b094860e86dee1d747dc2015"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXCFG_RX_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:gaa6ee4fc8b094860e86dee1d747dc2015"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa04279dfefec1d405197f608cee79abe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa04279dfefec1d405197f608cee79abe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXCFG_DEL_FCS_MASK</b>&#160;&#160;&#160;0x00000002</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXCFG_IGN_FCS_MASK</b>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="separator:gaf1748ccccd101b86b5c553d8dfa8815b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">USXGMII Auto negotiation register masks</div></td></tr>
<tr class="memitem:ga00e39d000759d301f34242592d158227"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga00e39d000759d301f34242592d158227"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANBYPASS_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
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<tr class="memitem:ga435af3ddd5f8f87a61a529f48ec645d4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga435af3ddd5f8f87a61a529f48ec645d4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANENABLE_MASK</b>&#160;&#160;&#160;0x00000020</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANMAINRESET_MASK</b>&#160;&#160;&#160;0x00000040</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANRESTART_MASK</b>&#160;&#160;&#160;0x00000080</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_MASK</b>&#160;&#160;&#160;0x00000700</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANA_MASK</b>&#160;&#160;&#160;0x00010000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANA_SPEED_MASK</b>&#160;&#160;&#160;0x0E000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANA_FD_MASK</b>&#160;&#160;&#160;0x10000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_ANACK_MASK</b>&#160;&#160;&#160;0x40000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_LINK_STS_MASK</b>&#160;&#160;&#160;0x80000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_10M_MASK</b>&#160;&#160;&#160;0x0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_100M_MASK</b>&#160;&#160;&#160;0x1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_1G_MASK</b>&#160;&#160;&#160;0x2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_10G_MASK</b>&#160;&#160;&#160;0x3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_2G5_MASK</b>&#160;&#160;&#160;0x4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_RATE_SHIFT</b>&#160;&#160;&#160;8</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_SPEED_SHIFT</b>&#160;&#160;&#160;25</td></tr>
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<tr><td colspan="2"><div class="groupHeader">RXMTU register masks</div></td></tr>
<tr class="memitem:gae3b679ced45fe7322a152052f5206876"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae3b679ced45fe7322a152052f5206876"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXMTU_MIN_JUM_MASK</b>&#160;&#160;&#160;0x000000FF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXMTU_MAX_JUM_MASK</b>&#160;&#160;&#160;0x7FFF0000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">RXBLSR register masks</div></td></tr>
<tr class="memitem:ga911d37be05c0edc67227b2b622ae7beb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga911d37be05c0edc67227b2b622ae7beb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_RXBLKLCK_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
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<tr><td colspan="2"><div class="groupHeader">TICK register masks</div></td></tr>
<tr class="memitem:gae2a745d4abde9ea5dd24157f77edea6c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae2a745d4abde9ea5dd24157f77edea6c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_TICK_STATEN_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AN status register masks</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_AN_COMP_MASK</b>&#160;&#160;&#160;0x00000004</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_USXGMII_AN_COMP_MASK</b>&#160;&#160;&#160;0x00010000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">AN ability register masks</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XXE_ANA_10GKR_MASK</b>&#160;&#160;&#160;0x00000004</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Reset and Address Filter (RAF) Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XAE_RAF_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:gad5711af97154aeef5f2175a70456fd6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#gad5711af97154aeef5f2175a70456fd6a">XXE_RAF_STATSRST_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gad5711af97154aeef5f2175a70456fd6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Statistics Counter Reset.  <a href="group__xxvethernet.html#gad5711af97154aeef5f2175a70456fd6a">More...</a><br/></td></tr>
<tr class="separator:gad5711af97154aeef5f2175a70456fd6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4fa9657c9445a73d4580ddc4c33f6507"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#ga4fa9657c9445a73d4580ddc4c33f6507">XXE_RAF_RXBADFRMEN_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:ga4fa9657c9445a73d4580ddc4c33f6507"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Bad Frame Enable.  <a href="group__xxvethernet.html#ga4fa9657c9445a73d4580ddc4c33f6507">More...</a><br/></td></tr>
<tr class="separator:ga4fa9657c9445a73d4580ddc4c33f6507"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit Inter-Frame Gap Adjustment Register (TFGP) bit definitions</div></td></tr>
<tr class="memitem:ga2cc8ef8e5952753a97d94a3ceb8becfb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#ga2cc8ef8e5952753a97d94a3ceb8becfb">XXE_TFGP_IFGP_MASK</a>&#160;&#160;&#160;0x0000007F</td></tr>
<tr class="memdesc:ga2cc8ef8e5952753a97d94a3ceb8becfb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit inter-frame gap adjustment value.  <a href="group__xxvethernet.html#ga2cc8ef8e5952753a97d94a3ceb8becfb">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Other Constant definitions used in the driver</div></td></tr>
<tr class="memitem:ga8f1033cd2bbe2db9e406d1c9d3f06684"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#ga8f1033cd2bbe2db9e406d1c9d3f06684">XXE_SPEED_10_GBPS</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:ga8f1033cd2bbe2db9e406d1c9d3f06684"><td class="mdescLeft">&#160;</td><td class="mdescRight">Speed of 10 Gbps.  <a href="group__xxvethernet.html#ga8f1033cd2bbe2db9e406d1c9d3f06684">More...</a><br/></td></tr>
<tr class="separator:ga8f1033cd2bbe2db9e406d1c9d3f06684"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga764c2fbd121e5eaa93a155ffac11ee66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#ga764c2fbd121e5eaa93a155ffac11ee66">XXE_LOOPS_TO_COME_OUT_OF_RST</a>&#160;&#160;&#160;10000</td></tr>
<tr class="memdesc:ga764c2fbd121e5eaa93a155ffac11ee66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of loops in the driver API to wait for before returning a failure case.  <a href="group__xxvethernet.html#ga764c2fbd121e5eaa93a155ffac11ee66">More...</a><br/></td></tr>
<tr class="separator:ga764c2fbd121e5eaa93a155ffac11ee66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba3e839e8b0ff28889dc79c9aa52d0a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xxvethernet.html#gaba3e839e8b0ff28889dc79c9aa52d0a6">XXE_RST_DELAY_LOOPCNT_VAL</a>&#160;&#160;&#160;10000</td></tr>
<tr class="memdesc:gaba3e839e8b0ff28889dc79c9aa52d0a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timeout in ticks used while checking if the core had come out of reset.  <a href="group__xxvethernet.html#gaba3e839e8b0ff28889dc79c9aa52d0a6">More...</a><br/></td></tr>
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